This application claims priority to an application entitled xe2x80x9cLAYOUT METHOD FOR BIT LINE SENSE AMPLIFIER DRIVERxe2x80x9d filed in the Korean Industrial Property Office on Jul. 20, 2001 and assigned Serial No. 2001-43790, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor circuits, and more particularly, to a layout method for a sense amplifier and a sense amplifier driver.
2. Description of the Related Art
In general, a bit line sense amplifier senses, amplifies, and outputs data of a memory cell selected by an address.
FIG. 1 is a circuit diagram of a conventional bit line sense amplifier. Referring to FIG. 1, a bit line sense amplifier 1 used in a DRAM includes a plurality of NMOS sense amplifiers 3 and a plurality of PMOS sense amplifiers 7 that are arranged symmetrically for maximization of characteristics. Hereinafter, for the convenience of explanation, one NMOS sense amplifier 3 and one PMOS sense amplifier 7 will be described.
The NMOS sense amplifier 3 includes NMOS transistors N1 and N3 for sensing data of bit lines BL0-BL2 and complementary bit lines BLB0-BLB2 respectively, and a first driver N5 for driving a ground voltage VSSA to a node ND in response to an enabling signal LANG. The PMOS sense amplifier 7 includes PMOS transistors P1 and P3 for sensing data of the bit lines BL0-BL2 and the complementary bit lines BLB0-BLB2 respectively, and a second driver P5 for driving a supply voltage VDD to the PMOS transistors P1 and P3 in response to an enabling signal LAPG.
FIG. 2 is a plan view of the layout of the conventional NMOS sense amplifier. Referring to FIGS. 1 and 2, the layout of the conventional NMOS sense amplifier 3 will be described below.
A gate G3 of the first driver N5 is arranged to have a ring shape, and the bit line BL0 is in contact with a gate G2 of the NMOS transistor N3 through a contact MC3, where the contact is a known electrical connecting means, and in contact with the NMOS transistor N1 through a contact MC1.
The complementary bit line BLB0 is in contact with a gate G1 of the NMOS transistor N1 through a contact MC4 and in contact with the NMOS transistor N3 through a contact MC2. The node ND to which the ground voltage VSSA is supplied is connected to an active region of the first driver N5 through a metal line LAB and a contact MC6.
Further, an enabling signal transmission line LANGL for transmitting the enabling signal LANG is in contact with the gate G3 of the first driver N5 through a contact MC5, and a ground voltage transmission line VSSAL is in contact with the active region of the first driver N5 through a contact MC7.
Resistance mismatch occurs in the conventional bit line sense amplifier 1 due to a difference in the distance from a gate of a column select line (not shown) to the bit line BL0 or to the complementary bit line BLB0.
In a case where the first driver N5 is laid out between the NMOS transistors N1 and N3, variation in a critical dimension (hereinafter referred to as CD) of gates occurs between the gates G1, G2, G4, and G5, which are laid out near the gate G3, and gates G6 and G7, which are laid out far from the gate G3.
Since a difference in distance occurs between the laid out gates, for example, between the gates G1 and G2 and the gates G6 and G7, a difference in coupling of the gate G3 of the first driver N5 occurs.
Further, since the contact MC6 is connected to the active region of the first driver N5, which has a large area, due to an increase in junction loading, noise occurs when the bit line sense amplifier senses data.
To solve the above problems, it is an objective of the present invention to provide a bit line sense amplifier having a layout in which variation in a critical dimension (CD) of gates of transistors for forming a bit line sense amplifier is minimized and in which an active region of a driver for supplying power to the bit line sense amplifier is reduced.
Accordingly, to achieve the above and other objects, there is provided a bit line sense amplifier. The bit line sense amplifier includes a first sense amplifier block in which a plurality of first sense amplifiers for sensing and amplifying data of a bit line or a complementary bit line are laid out, and first drivers for pulling down the bit line or the complementary bit line to a first voltage level, which is lower than a pre-charge voltage in response to a first control signal, and each of the first drivers is arranged outside the plurality of first sense amplifiers.
The bit line sense amplifier further includes a second sense amplifier block in which a plurality of second sense amplifiers for sensing and amplifying data of the bit line or the complementary bit line are laid out, and second drivers for pulling up the bit line or the complementary bit line to a second voltage level, which is higher than the pre-charge voltage, in response to a second control signal, and each of the second drivers is arranged outside the plurality of second sense amplifiers.
The bit line or the complementary bit line includes a global power supply transmission line arranged in the same direction as the bit line, and a local power supply transmission line electrically connected to the global power supply transmission line and arranged at a predetermined degree to the global power supply transmission line, and the bit line or the complementary bit line is pulled down to the first voltage level through the first drivers.
The first sense amplifier includes a first node, a first transistor having a gate connected to the complementary bit line, a first terminal connected to the bit line, and a second terminal connected to the first node, and a second transistor having a gate connected to the bit line, a first terminal connected to the complementary bit line, and a second terminal connected to the first node, and the first drivers include a third transistor having a gate that receives the first control signal, a first terminal connected to the first node, and a second terminal that receives the first voltage level, wherein the gate of the third transistor having a T-shape or an L-shape is laid out on a given active region, and wherein the first voltage level is transmitted to the second terminal of the third transistor through the global power supply transmission line laid out in the same direction as the bit line and the local power supply transmission line laid out perpendicular to the global power supply transmission line and is transmitted to the first node through the first terminal of the third transistor.
The bit line or the complementary bit line includes a global power supply transmission line arranged in the same direction as the bit line, and a local power supply transmission line electrically connected to the global power supply transmission line and arranged at a predetermined degree to the global power supply transmission line, and the bit line or the complementary bit line is pulled up to the second voltage level through the second drivers.
The second sense amplifier includes a second node, a fourth transistor having a gate connected to the complementary bit line, a first terminal connected to the bit line, and a second terminal connected to the first node, and a fifth transistor having a gate connected to the bit line, a first terminal connected to the complementary bit line, and a second terminal connected to the first node, and the second drivers include a sixth transistor having a gate that receives the second control signal, a first terminal connected to the first node, and a second terminal that receives the second voltage level, wherein the gate of the sixth transistor having a T-shape or an L-shape is laid out on a given active region, and wherein the second voltage level is transmitted to the second terminal of the sixth transistor through the global power supply transmission line laid out in the same direction as the bit line and the local power supply transmission line laid out perpendicular to the global power supply transmission line and is transmitted to the second node through the first terminal of the sixth transistor.